[klausimo] Debug vartai lygio modeliavimas erro for Altera "?

[etrobin]

Dear all,

When I run vartai lygio modeliavimas, radau viena klaida įvyksta, bet tai praeiti, kai RTL modeliavimas!Kaip aš galiu atsekti iki netlist klaidą?Ir kaip man žinoti Altera apex20ke_lcell elgesį?Ką aš pastebimas "regout" neteisingas, ir CLK darbas normalus ..........Thakn Jums už atsakymą!

<img src="http://www.edaboard.com/images/smiles/icon_biggrin.gif" alt="Very Happy" border="0" />========================================
netlist generuoja qu (at) rtus už ModelSim, prietaisas yra APEX20KE
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apex20ke_lcell \ u_my_design | u_my_sub_design | u_test | X1_1_ (
/ / Lygtis (-ai):
/ / \ U_my_design | u_my_sub_design | u_test | X1 [1] = \ u_my_design | u_my_sub_design | u_test | GO0_0 $ \ u_my_design | u_my_sub_design | u_test | GINFF [1] $ (\ u_my_design | u_my_sub_design | u_test | GO7_1)

. dataa (\ u_my_design | u_my_sub_design | u_test | GO7_1)
. datab (\ u_my_design | u_my_sub_design | u_test | GO0_0)
. datac (\ u_my_design1 | u_my_sub_design1 | u_oo)
. datad (\ u_my_design | u_my_sub_design | u_test | GINFF [1]),
. CIN (GND)
. cascin (Vcc)
. CLK (GND)
. aclr (GND)
. ena (Vcc)
. sclr (GND)
. sload (GND)
. devclrn (devclrn)
. devpor (devpor)
. combout (\ u_my_design | u_my_sub_design | u_test | X1 [1]),
. regout (),
. teismas (),
. cascout ());
/ / Synopsys translate_off
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_. operation_mode = "normal";
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_. packed_mode = "false";
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_. lut_mask = "39C6";
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_. output_mode = "comb_only";
/ / Synopsys translate_on

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